The present invention is generally related to semiconductor integrated circuits. More particularly, the present invention is related to a circuit element used in protection circuits of semiconductor integrated circuits and the like.
Integrated circuits and other semiconductor devices are susceptible to being damaged or completely destroyed by various electrostatic discharge (ESD) events and the like. Protection circuits are therefore advantageously included on chips to prevent and reduce damage from such events. More particularly, the protection circuits are formed and situated to absorb the electrostatic discharge and preclude the ESD event from damaging the functional or active circuit elements of the integrated circuit or other semiconductor device. The protection circuit elements are preferably adapted to carry considerable current during an ESD event, current which would otherwise damage or destroy the integrated circuit or other semiconductor device within which the protection circuit element is incorporated.
One of the protection circuit elements used for ESD protection is a parasitic n-p-n bipolar transistor, sometimes called a xe2x80x9csnapbackxe2x80x9d device. Snapback devices are easily manufacturable, have low leakage characteristics, and can carry considerable current during an ESD event, once the device xe2x80x9csnaps backxe2x80x9d into bipolar operation.
In modern semiconductor fabrication technologies such as shallow trench isolation (STI) technologies, the junction breakdown voltage, which triggers the snapback device into operation, has increased. At the same time, the breakdown voltages of sensitive active circuit elements which are desirably protected, are getting lower. The relatively higher breakdown voltage of the protection circuit element reduces its effectiveness by making it too difficult for the protection circuit element to become activated and prevent damage to active circuit elements. Circuit elements of the active device may therefore be destroyed by the ESD event before the protection circuit element turns on.
The current (I)/voltage(V) characteristics of a conventional snapback device is shown in FIG. 1. During an ESD event, both the current I and voltage V of the snapback device are increased. As the voltage on the conventional snapback device is increased with respect to the substrate in which the snapback device is formed, avalanche breakdown occurs when avalanche breakdown voltage VAB is exceeded. The avalanche breakdown region is shown as segment 2 of the I-V curve shown in FIG. 1. When the avalanche current becomes sufficiently high, the device goes into bipolar snapback and the voltage across the device drops. The trigger point for bipolar snapback is characterized by the trigger voltage and trigger current, Vt1 and It1, respectively. The lowest voltage at which the bipolar action can be sustained is called the xe2x80x9csnapback voltage,xe2x80x9d VSB. When in bipolar snapback mode as indicated by segment 6 of the I-V curve shown in FIG. 1, considerable current can be carried throughout the snapback device at a lowered voltage and without damage occurring to the active circuit elements of the integrated circuit. When in bipolar snapback mode 6, the snapback device essentially functions as an n-p-n bipolar transistor and carries additional current, such as may be generated by an ESD event, and which otherwise would travel through and damage or destroy active device components of the integrated circuit device. In this manner, the snapback device suppresses device damage. When current is increased further, damage to the active circuit elements of the integrated circuit will eventually occur. The highest point before the active components of the integrated are damaged, is characterized by the coordinates of voltage Vt2 and current It2.
In order to be effective and to provide protection, the snapback device must logically be triggered into snapback, bipolar mode before the active circuit components of the integrated circuit device become damaged. Generally speaking, the breakdown voltage of the snapback device must be lower than the breakdown voltages of the active circuit components. The avalanche breakdown voltage, VAB, is generally considered to be the breakdown voltage of the snapback device. The trigger voltage, Vt1, of the snapback device should desirably be lower than the breakdown voltages of the active current components to prevent active device damage from occurring before the trigger point is achieved. It is also desirable that voltage Vt1 not be much higher than the snapback voltage, VSB. Stated alternatively, the voltage differential between Vt1 and VSB is desirably minimized. It is also desirable that the snapback device is capable of carrying as much current as possible to prevent damage to active circuit components.
The device layout of a conventional snapback device is shown in FIG. 2. FIG. 2 shows a snapback device formed of two substantially similar structures 120. Each structure 120 includes an active area 124 which is preferably an N+ impurity region formed in a substrate and surrounded by a P-doped impurity region 130 also formed within the substrate. Each structure 120 includes a conductive film 122 formed over active area 124 and electrically coupled to active area 124 through contacts 126. The snapback device includes a width 128. One conductive layer 122 is electrically coupled to an input/output pad and the other conductive layer 122 is electrically coupled to a voltage source or ground source.
One conventional method for increasing the effectiveness of a snapback device is to increase width 128 to provide more protection. Since this increased width comes at the expense of real estate on an integrated circuit chip which otherwise could be used for active circuit components, this approach is generally not favored. A more favored approach is to provide several smaller snapback devices in parallel to provide increased protection against ESD damage. Referring back to FIG. 1, for parallel snapback devices to be effective, it is necessary that Vt2 is greater than Vt. This is to ensure that each of the snapback devices turns on and snaps back to bipolar mode, before voltage Vt2 is achieved in any one snapback device, thereby damaging and/or destroying the active component elements of the integrated circuit device. This is not achieved in the conventional snapback device described by the I/V curve of FIG. 1.
It is therefore desirable to provide a protection circuit element that includes a breakdown voltage that is lower than the breakdown voltages of the active circuit elements of the integrated circuit device in which the protection circuit element is incorporated. It is also desirable to provide such a protection circuit element which is capable of carrying considerable current and includes a trigger point that does not significantly exceed the snapback voltage, and a trigger voltage which is lower than the voltage at which damage occurs to the active devices which the protection circuit element is designed to protect. It is further desirable to provide such a protection circuit element which provides significant protection versus ESD damage, while minimizing the amount of substrate space occupied by the protection circuit element.
The present invention provides a snapback device including two active areas of one polarity formed within a substrate surface and separated by a substrate region of the opposite polarity. The snapback device is included within a semiconductor device. Each active area is partially overlapped by an overlap film which is separated from the active area by a dielectric film. The overlap film may be formed of a metal or a semiconductor material. Each overlap film and associated active area are electrically coupled to a conductive layer formed over the structure. One conductive layer is advantageously coupled to input/output terminals of the semiconductor device and the other is coupled to a ground source and/or power supply. The snapback device includes a reduced avalanche breakdown voltage and trigger point voltage which allows the device to snap back into bipolar mode such that it is capable of carrying additional current at a relatively low voltage. The snapback device thereby protects active circuit components from being subjected to the considerable current produced by ESD events and which would otherwise damage and/or destroy the integrated circuit device.